1. Field
This disclosure relates generally to semiconductor processing, and more specifically, to split gate devices.
2. Related Art
Split gate devices, which include both a select gate and a control gate, are typically used as bitcell storage devices within nonvolatile memory arrays. The use of a separate select gate for the bitcells in such arrays allows for improved isolation and reduced bitcell disturb during programming and reading of the bitcells. For example, program disturb is reduced for memory cells that are unselected but are either on the selected row or, in the alternative, on the selected column. Normally, cells on the selected row or the selected column are the most likely to be a problem for disturb regardless of the operation that is being performed on a selected cell. With the split gate memory cell having substantially solved the program disturb problem for cells on the selected rows or columns, a disturb problem with cells on unselected rows and unselected columns has become significant. One of the reasons is that the particular stress that is applied for cells on unselected rows and columns is applied for many more cycles than for a stress that is applied for cells on a selected row or column. Also, due to the length of the select gates and control gates, reduced drive current is obtained which degrades reading performance.